As integrated circuits and systems continue to advance and become more complex, effective and efficient power and thermal management of the integrated circuits and systems have become more and more critical in circuit design and implementation. In order to reduce the power consumption in integrated circuits and systems, these circuits and systems have been designed to operate at lower voltage levels. For example, integrated circuits and systems have been designed to operate at voltage levels such as 5 volts, 3.3 volts, or less provided by the power supply. However, some components or circuitry in these integrated circuits or systems require higher voltages to operate or function. For instance, flash electrically erasable programmable read only (flash EEPROM) memory devices that are used in computers or systems typically require voltage levels that are higher than that provided by the power supply to perform various operations such as read, erase, or programming operations. In order to generate the voltage levels required by the flash memory that is higher than that provided by the power supply, charge pump circuits are typically used to generate a higher voltage level from a lower voltage level source. Charge pump circuits typically contain multiple pump stages that are used to increase a lower voltage input to a higher voltage output through incremental voltage increase at each stage. Each of the multiple pump stages in the charge pump circuits typically uses one or more capacitors for storing and transferring charge to the next pump stage in order to increase the voltage level from one stage to the next stage. However, the required voltage levels at some stages, especially the final stages of the charge pump circuit, can exceed the stress or breakdown voltage limitation of a single capacitor used for storing and transferring charge. If the stress or breakdown voltage limitation of the single capacitor is exceeded, the maximum voltage level generated at those pump stages will be limited. To overcome this problem, two or more capacitors can be connected in series to reduce the voltage across each of the capacitors. Connecting two or more capacitors in series is also referred to as the stacked capacitor configuration. However, using two or more capacitors connected in series increases the die area of the charge pump circuit. Therefore it is not desirable to use any more capacitors in the charge pump circuit than the number that is required for the circuit to function properly. Moreover, in many charge pump circuits, the output node of the charge pump circuit can be driven from one voltage level that is required for one type of flash memory operation to another voltage level that is required for another type of flash memory operation resulting in a total voltage sweep that is greater than the breakdown voltage of each capacitor connected in series. For example, an output node of a negative charge pump circuit can go all the way down to −15 volts when the negative charge pump is running to +11 volts when it stops and gets initialized to a proper internal signal. In this instance, the total voltage sweep is 26 volts, which can be greater than the total maximum voltage that can be endured by the two capacitors connected in series.
Accordingly, there exists a need to effectively and efficiently balance the performance requirements, the power usage requirements, and the die areas of the charge pump circuits so that the required output voltage can be achieved without exceeding the stress limits of the capacitors used in the charge pump circuits and without unnecessary increase in the die area.